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| the mark shows major revised points. the m pd75p0016 replaces the m pd750008s internal mask rom with a one-time prom and features expanded rom capacity. because the m pd75p0016 supports programming by users, it is suitable for use in prototype testing for system development using the m pd750004, 750006, or 750008 products, and for use in small-lot production. detailed information about product features and specifications can be found in the following document m pd750008 user's manual: u10740e features compatible with m pd750008 memory capacity: ? prom : 16384 8 bits ? ram : 512 4 bits can operate in same power supply voltage as the mask rom version m pd750008 ? v dd = 2.2 to 5.5 v supports qtop? microcontroller remark qtop microcontroller is the general name for a total support service that includes imprinting, marking, screening, and verifying one-time prom single-chip microcontrollers offered by nec. ordering information part number package rom ( 8 bits) m pd75p0016cu 42-pin plastic shrink dip (600 mil, 1.778-mm pitch) 16384 m pd75p0016gb-3bs-mtx 44-pin plastic qfp (10 10 mm, 0.8-mm pitch) 16384 caution on-chip pull-up resistors by mask option cannot be provided. m pd75p0016 mos integrated circuit 4-bit single-chip microcontroller the information in this document is subject to change without notice. document no. u10328ej3v1ds00 (3rd edition) date published august 2000 n cp(k) printed in japan 1995 data sheet
m pd75p0016 2 data sheet u10328ej3v1ds00 function list item function instruction execution time ? 0.95, 1.91, 3.81, 15.3 m s (main system clock: at 4.19 mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (main system clock: at 6.0 mhz operation) ? 122 m s (subsystem clock: at 32.768 khz operation) on-chip memory prom 16384 8 bits ram 512 4 bits general register ? in 4-bit operation: 8 4 banks ? in 8-bit operation: 4 4 banks i/o port cmos input 8 connection of on-chip pull-up resistor specifiable by software: 7 cmos i/o 18 direct led drive capability connection of on-chip pull-up resistor specifiable by software: 18 n-ch open drain i/o 8 direct led drive capability 13 v withstand voltage total 34 timer 4 channels ? 8-bit timer/event counter: 1 channel ? 8-bit timer counter: 1 channel ? basic interval timer/watchdog timer: 1 channel ? watch timer: 1 channel serial interface ? 3-wire serial i/o mode ... switching of msb/lsb-first ? 2-wire serial i/o mode ? sbi mode bit sequential buffer (bsb) 16 bits clock output (pcl) ? f , 524, 262, 65.5 khz (main system clock: at 4.19 mhz operation) ? f , 750, 375, 93.8 khz (main system clock: at 6.0 mhz operation) buzzer output (buz) ? 2, 4, 32 khz (main system clock: at 4.19 mhz operation or subsystem clock: at 32.768 khz operation) ? 2.93, 5.86, 46.9 khz (main system clock: at 6.0 mhz operation) vectored interrupt external: 3 internal: 4 test input external: 1 internal: 1 system clock oscillation circuit ? main system clock oscillation ceramic/crystal oscillation circuit ? subsystem clock oscillation crystal oscillation circuit standby function stop/halt mode operating ambient temperature t a = C40 to +85?c supply voltage v dd = 2.2 to 5.5 v package 42-pin plastic shrink dip (600 mil, 1.778-mm pitch) 44-pin plastic qfp (10 10 mm, 0.8-mm pitch) m pd75p0016 3 data sheet u10328ej3v1ds00 table of contents 1. pin configuration ............................................................................................................ ............ 4 2. block diagram ................................................................................................................ ............. 6 3. pin functions ................................................................................................................ ................ 7 3.1 port pins ................................................................................................................... .................................. 7 3.2 non-port pins ............................................................................................................... .............................. 8 3.3 i/o circuits for pins ....................................................................................................... ............................ 9 3.4 handling of unused pins ..................................................................................................... ................... 11 4. switching between mk i and mk ii modes .......................................................................... 12 4.1 differences between mk i mode and mk ii mode ................................................................................ ... 12 4.2 setting of stack bank selection (sbs) register .............................................................................. ..... 13 5. differences between m pd75p0016 and m pd750004, 750006, and 750008 ...................... 14 6. memory configuration ......................................................................................................... .. 15 7. instruction set .............................................................................................................. ............ 17 8. one-time prom (program memory) write and verify ................................................... 28 8.1 operation modes for program memory write/verify ............................................................................ 2 8 8.2 steps in program memory write operation ..................................................................................... ..... 29 8.3 steps in program memory read operation ...................................................................................... ..... 30 8.4 one-time prom screening ..................................................................................................... ............... 31 9. electrical specifications .................................................................................................... .32 10. characteristic curves (reference value) .................................................................... 46 11. package drawings ............................................................................................................ ........ 48 12. recommended soldering conditions ................................................................................ 50 appendix a. function list of m pd75008, 750008, 75p0016 ....................................................... 51 appendix b. development tools ................................................................................................. 53 appendix c. related documents ................................................................................................ 57 m pd75p0016 4 data sheet u10328ej3v1ds00 p72/kr6 1 p13/ti0 33 p71/kr5 2 p00/int4 32 p70/kr4 3 p01/sck 31 p63/kr3 4 p02/so/sb0 30 p62/kr2 5 p03/si/sb1 29 p61/kr1 6 p80 28 p60/kr0 7 p81 27 p53/d7 8 p30/md0 26 p52/d6 9 p31/md1 25 p51/d5 10 p32/md2 24 p50/d4 11 p33/md3 23 p73/kr7 44 nc 12 p20/pto0 43 p43/d3 13 p21/pto1 42 p42/d2 14 p22/pcl 41 p41/d1 15 p23/buz 40 p40/d0 16 v dd 39 v ss 17 v pp note 38 xt1 18 p10/int0 37 xt2 19 p11/int1 36 reset 20 p12/int2 35 x1 21 nc 34 x2 22 1. pin configuration (top view) 42-pin plastic shrink dip (600 mil, 1.778-mm pitch) m pd75p0016cu note directly connect v pp to v dd in the normal operation mode. 44-pin plastic qfp (10 10 mm, 0.8-mm pitch) m pd75p0016gb-3bs-mtx note directly connect v pp to v dd in the normal operation mode. xt1 1 v ss 42 xt2 2 p40/d0 41 reset 3 p41/d1 40 x1 4 p42/d2 39 x2 5 p43/d3 38 p33/md3 6 p50/d4 37 p32/md2 7 p51/d5 36 p31/md1 8 p52/d6 35 p30/md0 9 p53/d7 34 p81 10 p60/kr0 33 p80 11 p61/kr1 32 p03/si/sb1 12 p62/kr2 31 p02/so/sb0 13 p63/kr3 30 p01/sck 14 p70/kr4 29 p00/int4 15 p71/kr5 28 p13/ti0 16 p72/kr6 27 p12/int2 17 p73/kr7 26 p11/int1 18 p20/pto0 25 p10/int0 19 p21/pto1 24 v pp note 20 p22/pcl 23 v dd 21 p23/buz 22 m pd75p0016 5 data sheet u10328ej3v1ds00 pin identifications p00-p03 : port0 sck : serial clock p10-p13 : port1 si : serial input p20-p23 : port2 so : serial output p30-p33 : port3 sb0, sb1 : serial data bus 0,1 p40-p43 : port4 reset : reset p50-p53 : port5 ti0 : timer input 0 p60-p63 : port6 pto0, pto1 : programmable timer output 0, 1 p70-p73 : port7 buz : buzzer clock p80, p81 : port8 pcl : programmable clock kr0-kr7 : key return 0-7 int0, 1, 4 : external vectored interrupt 0, 1, 4 v dd : positive power supply int2 : external test input 2 v ss : ground x1, x2 : main system clock oscillation 1, 2 v pp : programming power supply xt1, xt2 : subsystem clock oscillation 1, 2 nc : no connection md0-md3 : mode selection 0-3 d0-d7 : data bus 0-7 m pd75p0016 6 data sheet u10328ej3v1ds00 bit seq. buffer (16) port0 p00-p03 4 port1 port2 4 port3 p30/md0-p33/md3 4 port4 p40/d0-p43/d3 4 port5 p50/d4-p53/d7 4 port6 p60-p63 4 v ss v dd reset v pp cpu clock f stand by control x2 x1 xt2 xt1 system clock generator main sub clock divider clock output control fx/2 n pcl/p22 general register data memory (ram) 512 4 bits bank sbs sp (8) cy alu program counter (14) program memory (prom) 16384 8 bits decode and control basic interval timer/ watchdog timer ti0/p13 intbt 8-bit timer/event counter #0 pto0/p20 intt0 8-bit timer counter #1 intt1 clocked serial interface si/sb1/p03 interrupt control int0/p10 so/sb0/p02 sck/p01 int1/p11 int2/p12 int4/p00 kr0/p60- kr7/p73 watch timer 8 port7 p70-p73 4 port8 p80, p81 2 p10-p13 4 p20-p23 pto1/p21 intcsi intw buz/p23 tout0 tout0 2. block diagram m pd75p0016 7 data sheet u10328ej3v1ds00 3. pin functions 3.1 port pins pin name i/o shared by function 8-bit when i/o circuit i/o reset type note 1 p00 i int4 this is a 4-bit input port (port0). input for p01 to p03, on-chip pull-up resistor connections p01 i/o sck are software-specifiable in 3-bit units. m pd75p0016 8 data sheet u10328ej3v1ds00 3.2 non-port pins pin name i/o shared by function when i/o circuit reset type note 1 ti0 i p13 external event pulse input to timer/event counter input -c pto0 o p20 timer/event counter output input e-b pto1 p21 timer counter output pcl p22 clock output buz p23 outputs any frequency (for buzzer or system clock trimming) sck i/o p01 serial clock i/o input m pd75p0016 9 data sheet u10328ej3v1ds00 3.3 i/o circuits for pins the i/o circuits for the m pd75p0016s pin are shown in schematic diagrams below. in v dd p-ch n-ch v dd p-ch n-ch out data output disable in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type a v dd p-ch p.u.r. enable p.u.r. p.u.r. : pull-up resistor in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type b cmos standard input buffer push-pull output that can be set to high impedance output (with both p-ch and n-ch off). schmitt trigger input with hysteresis characteristics. ( continued ) type a type d type e-b type b type b-c type f-a m pd75p0016 10 data sheet u10328ej3v1ds00 p.u.r. p-ch p.u.r. : pull-up resistor data output disable in/out v dd p.u.r. enable n-ch type m-e type m-c type f-b p.u.r. p-ch in/out n-ch p-ch v dd p.u.r. enable data output disable output disable (n) output disable (p) p.u.r. : pull-up resistor v dd n-ch (+13 v) in/out p-ch v dd note pull-up resistor that operates only when an input instruction has been executed. (current flows from v dd to the pins when at low level) data output disable input instruction (+13 v) p.u.r. note voltage limitation circuit m pd75p0016 11 data sheet u10328ej3v1ds00 input mode : individually connect to v ss or v dd via resistor output mode : open 3.4 handling of unused pins table 3-1. handling of unused pins pin recommended connection p00/int4 connect to v ss or v dd p01/sck individually connect to v ss or v dd via resistor p02/so/sb0 p03/si/sb1 connect to v ss p10/int0-p12/int2 connect to v ss or v dd p13/ti0 p20/pto0 p21/pto1 p22/pcl p23/buz p30/md0-p33/md3 p40/d0-p43/d3 connect to v ss p50/d4-p53/d7 p60/kr0-p63/kr3 p70/kr4-p73/kr7 p80, p81 xt1 note connect to v ss xt2 note open v pp make sure to connect directly to v dd note when the subsystem clock is not used, set sos. 0 to 1 (not to use the internal feedback resistor). input mode : individually connect to v ss or v dd via resistor output mode : open m pd75p0016 12 data sheet u10328ej3v1ds00 4. switching between mk i and mk ii modes setting a stack bank selection (sbs) register for the m pd75p0016 enables the program memory to be switched between the mk i mode and the mk ii mode. this capability enables the evaluation of the m pd750004, 750006, or 750008 using the m pd75p0016. when the sbs bit 3 is set to 1: sets mk i mode (corresponds to mk i mode of m pd750004, 750006, and 750008) when the sbs bit 3 is set to 0: sets mk ii mode (corresponds to mk ii mode of m pd750004, 750006, and 750008) 4.1 differences between mk i mode and mk ii mode table 4-1 lists the differences between the mk i mode and the mk ii mode of the m pd75p0016. table 4-1. differences between mk i mode and mk ii mode item mk i mode mk ii mode program counter pc 13-0 program memory (bytes) 16384 data memory (bits) 512 4 stack stack bank selectable from memory banks 0 and 1 stack bytes 2 bytes 3 bytes instruction bra !addr1 none provided calla !addr1 instruction call !addr 3 machine cycles 4 machine cycles execution time callf !faddr 2 machine cycles 3 machine cycles supported mask rom versions and mk i mode of m pd750004, 750006, and mk ii mode of m pd750004, 750006, and mode 750008 750008 caution the mk ii mode supports a program area which exceeds 16k bytes in the 75x and 75xl series. this mode enhances the software compatibility with products which have more than 16k bytes. when the mk ii mode is selected, the number of stack bytes used in execution of a subroutine call instruction increases by 1 per stack for the usable area compared to the mk i mode. furthermore, when a call !addr, or callf !faddr instruction is used, each instruction takes another machine cycle. therefore, when more importance is attached to ram utilization or throughput than software compatibility, use the mk i mode. m pd75p0016 13 data sheet u10328ej3v1ds00 sbs3 sbs2 sbs1 sbs0 f84h address 3 2 1 0 sbs 0 0 1 1 0 1 0 1 symbol stack area specification memory bank 0 memory bank 1 0 be sure to set 0 for bit 2. 0 1 mk ii mode mk i mode mode selection specification setting prohibited 4.2 setting of stack bank selection (sbs) register use the stack bank selection register to switch between the mk i mode and the mk ii mode. figure 4-1 shows the format for doing this. the stack bank selection register is set using a 4-bit memory manipulation instruction. when using the mk i mode, be sure to initialize the stack bank selection register to 100 b note at the beginning of the program. when using the mk ii mode, be sure to initialize it to 000 b note . note set the desired value for . figure 4-1. format of stack bank selection register caution sbs3 is set to 1 after reset input, and consequently the cpu operates in the mk i mode. when using instructions for the mk ii mode, set sbs3 to 0 to enter the mk ii mode before using the instructions. m pd75p0016 14 data sheet u10328ej3v1ds00 5. differences between m pd75p0016 and m pd750004, 750006, and 750008 the m pd75p0016 replaces the internal mask rom in the m pd750004, 750006, and 750008 with a one-time prom and features expanded rom capacity. the m pd75p0016s mk i mode supports the mk i mode in the m pd750004, 750006, and 750008 and the m pd75p0016s mk ii mode supports the mk ii mode in the m pd750004, 750006, and 750008. table 5-2 lists differences among the m pd75p0016 and the m pd750004, 750006, and 750008. be sure to check the differences between corresponding versions beforehand, especially when a prom version is used for debugging or prototype testing of application systems and later the corresponding mask rom version is used for full-scale production. please refer to the m pd750008 user's manual (u10740e) for details on cpu functions and on-chip hardware. table 5-1. differences between m pd75p0016 and m pd750004, 750006, and 750008 item m pd750004 m pd750006 m pd750008 m pd75p0016 program counter 12-bit 13-bit 14-bit program memory (bytes) mask rom mask rom mask rom one-time prom 4096 6144 8192 16384 data memory ( 4 bits) 512 mask options pull-up resistor for yes (on-chip/not on-chip can be specified.) no (on-chip not port 4 and port 5 possible) wait time when yes (2 17 /f x or 2 15 /f x ) note no (fixed at 2 15 /f x ) note reset feedback resistor yes (can select usable or unusable.) no (usable) for subsystem clock pin connection pins 6-9 (cu) p33-p30 p33/md3-p30/md0 pins 23-26 (gb) pin 20 (cu) ic v pp pin 38 (gb) pins 34-37 (cu) p53-p50 p53/d7-p50/d4 pins 8-11 (gb) pins 38-41 (cu) p43-p40 p43/d3-p40/d0 pins 13-16 (gb) other noise resistance and noise radiation may differ due to the different circuit complexities and mask layouts. note 2 17 /f x : 21.8 ms @ 6.0 mhz, 31.3 ms @ 4.19 mhz 2 15 /f x : 5.46 ms @ 6.0 mhz, 7.81 ms @ 4.19 mhz caution noise resistance and noise radiation are different in prom version and mask rom versions. if using a mask rom version instead of the prom version for processes between prototype development and full production, be sure to fully evaluate the cs of the mask rom version (not es). m pd75p0016 15 data sheet u10328ej3v1ds00 6. memory configuration figure 6-1. program memory map note can be used only at mk ii mode. remark for instructions other than those noted above, the br pcde and br pcxa instructions can be used to branch to addresses with changes in the pcs lower 8 bits only. mbe mbe mbe mbe mbe mbe mbe rbe rbe rbe rbe rbe rbe rbe internal reset start address (higher 6 bits) internal reset start address (lower 8 bits) intbt/int4 start address (higher 6 bits) intbt/int4 start address (lower 8 bits) int0 start address (higher 6 bits) int0 start address (lower 8 bits) int1 start address (higher 6 bits) int1 start address (lower 8 bits) intcsi start address (higher 6 bits) intcsi start address (lower 8 bits) intt0 start address (higher 6 bits) intt0 start address (lower 8 bits) intt1 start address (higher 6 bits) intt1 start address (lower 8 bits) reference table for geti instruction 0000h 0002h 0004h 0006h 0008h 000ah 000ch 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 3fffh callf !faddr instruction entry address branch address for the following instructions branch/call address by geti br $addr instruction relative branch address (C15 to C1, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address 76 0 ? br bcde ? br bcxa ? br !addr ? call !addr ? bra !addr1 ? calla !addr1 note note m pd75p0016 16 data sheet u10328ej3v1ds00 (32 4) 256 4 (224 4) 256 4 128 4 0 1 15 000h 01fh 020h 0ffh 100h 1ffh f80h fffh general register area data area static ram (512 4) stack area peripheral hardware area data memory memory bank unimplemented note figure 6-2. data memory map note for the stack area, one memory bank can be selected from memory bank 0 or 1. m pd75p0016 17 data sheet u10328ej3v1ds00 7. instruction set (1) representation and coding formats for operands in the instructions operand area, use the following coding format to describe operands corresponding to the instructions operand representations (for further description, refer to the ra75x assembler package users manual [eeu-1363] ). when there are several codes, select and use just one. upper-case letters, and + and C symbols are key words that should be entered as they are. for immediate data, enter an appropriate numerical value or label. instead of mem, fmem, pmem, bit, etc, a register flag symbol can be described as a label descriptor. (for further description, refer to the m pd750008 user's manual [u10740e] ) labels that can be entered for fmem and pmem are restricted. representation coding format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp xa, bc, de, hl, xa, bc, de, hl rp1 bc, de, hl, xa, bc, de, hl rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h-fbfh, ff0h-fffh immediate data or label pmem fc0h-fffh immediate data or label addr 0000h-3fffh immediate data or label addr1 0000h-3fffh immediate data or label (in mk ii mode only) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h-7fh immediate data (however, bit0 = 0) or label portn port0-port8 iexxx iebt, iecsi, iet0, iet1, ie0-ie2, ie4, iew rbn rb0-rb3 mbn mb0, mb1, mb15 note when processing 8-bit data, only even addresses can be specified. m pd75p0016 18 data sheet u10328ej3v1ds00 (2) operation legend a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : expansion register pair (xa) bc : expansion register pair (bc) de : expansion register pair (de) hl : expansion register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 8) ime : interrupt master enable flag ips : interrupt priority select register ie : interrupt enable flag rbs : register bank select register mbs : memory bank select register pcc : processor clock control register . : delimiter for address and bit ( ) : contents of address h : hexadecimal data m pd75p0016 19 data sheet u10328ej3v1ds00 (3) description of symbols used in addressing area remarks 1. mb indicates access-enabled memory banks. 2. in area *2, mb = 0 for both mbe and mbs. 3. in areas *4 and *5, mb = 15 for both mbe and mbs. 4. areas *6 to *11 indicate corresponding address-enabled areas. mb = 0 (000h-07fh) mb = 15 (f80h-fffh) mb = mbs mbs = 0, 1, 15 mb = mbe ? mbs mbs = 0, 1, 15 *1 mb = 0 *2 mbe = 1 : mbe = 0 : *3 mb = 15, fmem = fb0h-fbfh, ff0h-fffh mb = 15, pmem = fc0h-fffh addr = 0000h-3fffh *4 *5 *6 addr, addr1 = *7 (current pc) C15 to (current pc) C1 (current pc) +2 to (current pc) +16 *8 caddr = 0000h-0fffh (pc 13 , 12 = 00b) or 1000h-1fffh (pc 13 , 12 = 01b) or 2000h-2fffh (pc 13 , 12 = 10b) or 3000h-3fffh (pc 13 , 12 = 11b) faddr = 0000h-07ffh taddr = 0020h-007fh addr1 = 0000h-3fffh (mk ii mode only) *9 *10 *11 program memory addressing data memory addressing m pd75p0016 20 data sheet u10328ej3v1ds00 (4) description of machine cycles s indicates the number of machine cycles required for skipping of skip-specified instructions. the value of s varies as shown below. ? no skip .......................................................................... s = 0 ? skipped instruction is 1-byte or 2-byte instruction ......... s = 1 ? skipped instruction is 3-byte instruction note ................. s = 2 note 3-byte instructions: br !addr, bra !addr1, call !addr, calla !addr1 caution the geti instruction is skipped for one machine cycle. one machine cycle equals one cycle (= t cy ) of the cpu clock f . use the pcc setting to select among four cycle times. m pd75p0016 21 data sheet u10328ej3v1ds00 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition transfer mov a, # n4 1 1 a n4 string-effect a reg1, # n4 2 2 reg1 n4 xa, # n8 2 2 xa n8 string-effect a hl, # n8 2 2 hl n8 string-effect b rp2, # n8 2 2 rp2 n8 a, @hl 1 1 a (hl) *1 a, @hl+ 1 2 + s a (hl), then l l + 1 *1 l = 0 a, @hlC 1 2 + s a (hl), then l l C 1 *1 l = fh a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 @hl, a 1 1 (hl) a*1 @hl, xa 2 2 (hl) xa *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 mem, a 2 2 (mem) a*3 mem, xa 2 2 (mem) xa *3 a, reg 2 2 a reg xa, rp 2 2 xa rp reg1, a 2 2 reg1 a rp1, xa 2 2 rp1 xa xch a, @hl 1 1 a (hl) *1 a, @hl+ 1 2 + s a (hl), then l l + 1 *1 l = 0 a, @hlC 1 2 + s a (hl), then l l C 1 *1 l = fh a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 a, reg1 1 1 a reg1 xa, rp 2 2 xa rp table movt xa, @pcde 1 3 xa (pc 13-8 + de) rom reference xa, @pcxa 1 3 xa (pc 13-8 + xa) rom xa, @bcde 1 3 xa (bcde) rom note *6 xa, @bcxa 1 3 xa (bcxa) rom note *6 note as for the b register, only the lower 2 bits are valid. m pd75p0016 22 data sheet u10328ej3v1ds00 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition bit transfer mov1 cy, fmem.bit 2 2 cy (fmem.bit) *4 cy, pmem.@l 2 2 cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 2 2 cy (h + mem 3-0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) cy *4 pmem.@l, cy 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy *5 @h + mem.bit, cy 2 2 (h + mem 3-0 .bit) cy *1 operation adds a, #n4 1 1 + s a a + n4 carry xa, #n8 2 2 + s xa xa + n8 carry a, @hl 1 1 + s a a + (hl) *1 carry xa, rp 2 2 + s xa xa + rp carry rp1, xa 2 2 + s rp1 rp1 + xa carry addc a, @hl 1 1 a, cy a + (hl) + cy *1 xa, rp 2 2 xa, cy xa + rp + cy rp1, xa 2 2 rp1, cy rp1 + xa + cy subs a, @hl 1 1 + s a a C (hl) *1 borrow xa, rp 2 2 + s xa xa C rp borrow rp1, xa 2 2 + s rp1 rp1 C xa borrow subc a, @hl 1 1 a, cy a C (hl) C cy *1 xa, rp 2 2 xa, cy xa C rp C cy rp1, xa 2 2 rp1, cy rp1 C xa C cy and a, #n4 2 2 a a ^ n4 a, @hl 1 1 a a ^ (hl) *1 xa, rp 2 2 xa xa ^ rp rp1, xa 2 2 rp1 rp1 ^ xa or a, #n4 2 2 a a v n4 a, @hl 1 1 a a v (hl) *1 xa, rp 2 2 xa xa v rp rp1, xa 2 2 rp1 rp1 v xa xor a, #n4 2 2 a a v n4 a, @hl 1 1 a a v (hl) *1 xa, rp 2 2 xa xa v rp rp1, xa 2 2 rp1 rp1 v xa m pd75p0016 23 data sheet u10328ej3v1ds00 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition accumulator rorc a 1 1 cy a 0 , a 3 cy, a n-1 a n manipulate not a 2 2 a a increment/ incs reg 1 1 + s reg reg + 1 reg = 0 decrement rp1 1 1 + s rp1 rp1 + 1 rp1 = 00h @hl 2 2 + s (hl) (hl) + 1 *1 (hl) = 0 mem 2 2 + s (mem) (mem) + 1 *3 (mem) = 0 decs reg 1 1 + s reg reg C 1 reg = fh rp 2 2 + s rp rp C 1 rp = ffh compare ske reg, #n4 2 2 + s skip if reg = n4 reg = n4 @hl, #n4 2 2 + s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1 + s skip if a = (hl) *1 a = (hl) xa, @hl 2 2 + s skip if xa = (hl) *1 xa = (hl) a, reg 2 2 + s skip if a = reg a = reg xa, rp 2 2 +s skip if xa = rp xa = rp carry flag set1 cy 1 1 cy 1 manipulate clr1 cy 1 1 cy 0 skt cy 1 1 + s skip if cy = 1 cy = 1 not1 cy 1 1 cy cy m pd75p0016 24 data sheet u10328ej3v1ds00 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition memory bit set1 mem.bit 2 2 (mem.bit) 1*3 manipulate fmem.bit 2 2 (fmem.bit) 1 *4 pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) 1 *5 @h + mem.bit 2 2 (h + mem 3-0 .bit) 1*1 clr1 mem.bit 2 2 (mem.bit) 0 *3 fmem.bit 2 2 (fmem.bit) 0 *4 pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) 0 *5 @h + mem.bit 2 2 (h + mem 3-0 .bit) 0*1 skt mem.bit 2 2 + s skip if(mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2 + s skip if(fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if(pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 *5 (pmem.@l) = 1 @h + mem.bit 2 2 + s skip if(h + mem 3-0 .bit) = 1 *1 (@h + mem.bit) = 1 skf mem.bit 2 2 + s skip if(mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2 + s skip if(fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2 + s skip if(pmem 7-2 + l 3-2 .bit(l 1-0 )) = 0 *5 (pmem.@l) = 0 @h + mem.bit 2 2 + s skip if(h + mem 3-0 .bit) = 0 *1 (@h + mem.bit) = 0 sktclr fmem.bit 2 2 + s skip if(fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if(pmem 7-2 + l 3-2 .bit (l 1-0 )) = 1 and clear *5 (pmem.@l) = 1 @h + mem.bit 2 2 + s skip if(h + mem 3-0 .bit) = 1 and clear *1 (@h + mem.bit) = 1 and1 cy, fmem.bit 2 2 cy cy ^ (fmem.bit) *4 cy, pmem.@l 2 2 cy cy ^ (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 2 2 cy cy ^ (h + mem 3-0 .bit) *1 or1 cy, fmem.bit 2 2 cy cy v (fmem.bit) *4 cy, pmem.@l 2 2 cy cy v (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 2 2 cy cy v (h + mem 3-0 .bit) *1 xor1 cy, fmem.bit 2 2 cy cy v (fmem.bit) *4 cy, pmem.@l 2 2 cy cy v (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 2 2 cy cy v (h + mem 3-0 .bit) *1 m pd75p0016 25 data sheet u10328ej3v1ds00 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition branch br note 1 addr pc 13-0 addr *6 assembler selects the most appropriate instruction among the following: ? br !addr ? brcb !caddr ? br $addr addr1 pc 13-0 addr1 *11 assembler selects the most appropriate instruction among the following: ? bra !addr1 ? br !addr ? brcb !caddr ? br $addr1 !addr 3 3 pc 13-0 addr *6 $addr 1 2 pc 13-0 addr *7 $addr1 1 2 pc 13-0 addr1 pcde 2 3 pc 13-0 pc 13-8 + de pcxa 2 3 pc 13-0 pc 13-8 + xa bcde 2 3 pc 13-0 bcde note 2 *6 bcxa 2 3 pc 13-0 bcxa note 2 *6 bra note 1 !addr1 3 3 pc 13-0 addr1 *11 brcb !caddr 2 2 pc 13-0 pc 13, 12 + caddr 11-0 *8 notes 1. shaded areas indicate support for the mk ii mode only. other areas indicate support for the mk i mode only. 2. as for the b register, only the lower 2 bits are valid. m pd75p0016 26 data sheet u10328ej3v1ds00 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition subroutine calla note !addr1 3 3 (sp C 5) 0, 0, pc 13 , 12 *11 stack control (sp C 6)(sp C 3)(sp C 4) pc 11-0 (sp C 2) , , mbe, rbe pc 13C0 addr1, sp sp C 6 call note !addr 3 3 (sp C 4)(sp C 1)(sp C 2) pc 11-0 *6 (sp C 3) (mbe, rbe, pc 13, 12 ) pc 13C0 addr, sp sp C 4 4 (sp C 5) 0, 0, pc 13 , 12 (sp C 6)(sp C 3)(sp C 4) pc 11-0 (sp C 2) , , mbe, rbe pc 13-0 addr, sp sp C 6 callf note !faddr 2 2 (sp C 4)(sp C 1)(sp C 2) pc 11-0 *9 (sp C 3) (mbe, rbe, pc 13, 12 ) pc 13-0 000 + faddr, sp sp C 4 3 (sp C 5) 0, 0, pc 13 , 12 (sp C 6)(sp C 3)(sp C 4) pc 11-0 (sp C 2) , , mbe, rbe pc 13-0 000 + faddr,sp sp C 6 ret note 1 3 (mbe, rbe, pc 13, 12 ) (sp + 1) pc 11-0 ? (sp)(sp + 3)(sp + 2) sp sp + 4 , , mbe, rbe (sp + 4) 0, 0, pc 13-12 (sp + 1) pc 11-0 (sp)(sp + 3)(sp + 2) sp sp + 6 rets note 1 3 + s (mbe, rbe, pc 13, 12 ) (sp + 1) unconditional pc 11-0 (sp)(sp + 3)(sp + 2) sp sp + 4 then skip unconditionally , , mbe, rbe (sp + 4) 0, 0, pc 13-12 (sp + 1) pc 11-0 (sp)(sp + 3)(sp + 2) sp sp + 6 then skip unconditionally reti note 1 3 mbe, rbe, pc 13, 12 (sp + 1) pc 11-0 (sp)(sp + 3)(sp + 2) psw (sp + 4)(sp + 5), sp sp + 6 0, 0, pc 13, 12 (sp + 1) pc 11-0 (sp)(sp + 3)(sp + 2) psw (sp + 4)(sp + 5), sp sp + 6 note shaded areas indicate support for the mk ii mode only. other areas indicate support for the mk i mode only. m pd75p0016 27 data sheet u10328ej3v1ds00 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - group mnemonic operand no. of machine operation addressing skip bytes cycle area condition subroutine push rp 1 1 (sp C 1)(sp C 2) rp, sp sp C 2 stack control bs 2 2 (sp C 1) mbs, (sp C 2) rbs, sp sp C 2 pop rp 1 1 rp (sp + 1)(sp), sp sp + 2 bs 2 2 mbs (sp + 1), rbs (sp), sp sp + 2 interrupt ei 2 2 ime(ips.3) 1 control ie 22ie 1 di 2 2 ime(ips.3) 0 ie 22ie 0 i/o in note 1 a, portn 2 2 a portn (n = 0 - 8) xa, portn 2 2 xa portn +1 , portn (n = 4, 6) out note 1 portn, a 2 2 portn a (n = 2 - 8) portn, xa 2 2 portn +1 , portn xa (n = 4, 6) cpu control halt 2 2 set halt mode(pcc.2 1) stop 2 2 set stop mode(pcc.3 1) nop 1 1 no operation special sel rbn 2 2 rbs n (n = 0 - 3) mbn 2 2 mbs n (n = 0, 1, 15) geti note 2, 3 taddr 1 3 ? when using tbr instruction *10 pc 13-0 (taddr) 5-0 + (taddr + 1) ? when using tcall instruction (sp C 4)(sp C 1)(sp C 2) pc 11-0 (sp C 3) mbe, rbe, pc 13, 12 pc 13-0 (taddr) 5-0 + (taddr + 1) sp sp C 4 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr + 1) instructions instruction 1 3 ? when using tbr instruction *10 pc 13-0 (taddr) 5-0 + (taddr + 1) 4 ? when using tcall instruction (sp C 5) 0, 0, pc 13, 12 (sp C 6)(sp C 3)(sp C 4) pc 11-0 (sp C 2) , , mbe, rbe pc 13-0 (taddr) 5-0 + (taddr + 1) sp sp C 6 3 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr + 1) instructions instruction notes 1. before executing the in or out instruction, set mbe to 0 or 1 and set mbs to 15. 2. tbr and tcall are assembler directives for the geti instructions table definitions. 3. shaded areas indicate support for the mk ii mode only. other areas indicate support for the mk i mode only. m pd75p0016 28 data sheet u10328ej3v1ds00 8. one-time prom (program memory) write and verify the program memory in the m pd75p0016 is a 16384 8-bit electronic write-enabled one-time prom. the pins listed in the table below are used for this proms write/verify operations. clock input from the x1 pins is used instead of address input as a method for updating addresses. pin name function v pp pin (usually v dd ) where programming voltage is applied during program memory write/verify x1, x2 clock input pin for address updating during program memory write/verify. input the x1 pins inverted signal to the x2 pin. md0/p30-md3/p33 operation mode selection pin for program memory write/verify d0/p40-d3/p43 (lower 4) 8-bit data i/o pin for program memory write/verify d4/p50-d7/p53 (higher 4) v dd pin where power supply voltage is applied. power voltage range for normal operation is 2.2 to 5.5 v. apply 6.0 v for program memory write/verify. caution pins not used for program memory write/verify should be processed as follows. ? all unused pins except xt2 ...... connect to vss via a pull-down resistor ? xt2 pin ........................................ leave open 8.1 operation modes for program memory write/verify when +6 v is applied to the m pd75p0016s v dd pin and +12.5 v is applied to its v pp pin, program write/verify modes are in effect. furthermore, the following detailed operation modes can be specified by setting pins md0 to md3 as shown below. operation mode specification operation mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l zero-clear program memory address l h h h write mode l l h h verify mode h h h program inhibit mode remark : l or h m pd75p0016 29 data sheet u10328ej3v1ds00 v pp v dd v dd + 1 v dd v pp v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 x repetitions write verify additional write address increment data input data output data input 8.2 steps in program memory write operation high-speed program memory write can be executed via the following steps. (1) pull down unused pins to v ss via resistors. set the x1 pin to low. (2) apply +5 v to the v dd and v pp pins. (3) wait 10 m s. (4) zero-clear mode for program memory addresses. (5) apply +6 v to v dd and +12.5 v power to v pp . (6) write data using 1-ms write mode. (7) verify mode. if write is verified, go to step (8) and if write is not verified, go back to steps (6) and (7). (8) x [= number of write operations from steps (6) and (7)] 1 ms additional write (9) 4 pulse inputs to the x1 pin updates (increments +1) the program memory address. (10) repeat steps (6) to (9) until the last address is completed. (11) zero-clear mode for program memory addresses. (12) apply +5 v to the v dd and v pp pins. (13) power supply off the following diagram illustrates steps (2) to (9). m pd75p0016 30 data sheet u10328ej3v1ds00 8.3 steps in program memory read operation the m pd75p0016 can read out the program memory contents via the following steps. (1) pull down unused pins to v ss via resistors. set the x1 pin to low. (2) apply +5 v to the v dd and v pp pins. (3) wait 10 m s. (4) zero-clear mode for program memory addresses. (5) apply +6 v power to v dd and +12.5 v to v pp . (6) verify mode. when a clock pulse is input to the x1 pin, data is output sequentially to one address at a time based on a cycle of four pulse inputs. (7) zero-clear mode for program memory addresses. (8) apply +5 v power to the v dd and v pp pins. (9) power supply off the following diagram illustrates steps (2) to (7). v pp v dd v dd + 1 v dd v pp v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 data output data output md0/p30 md2/p32 md3/p33 md1/p31 l m pd75p0016 31 data sheet u10328ej3v1ds00 8.4 one-time prom screening due to its structure, the one-time prom cannot be fully tested before shipment by nec. therefore, nec recommends the screening process, that is, after the required data is written to the prom and the prom is stored under the high- temperature conditions shown below, the prom should be verified. storage temperature storage time 125?c 24 hours at present, a fee is charged by nec for one-time prom after-programming imprinting, screening, and verify service for the qtop microcontroller. for details, contact your sales representative. m pd75p0016 32 data sheet u10328ej3v1ds00 9. electrical specifications absolute maximum ratings (t a = 25?c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to + 7.0 v prom supply voltage v pp C0.3 to + 13.5 v input voltage v i1 other than port 4, 5 C0.3 to v dd + 0.3 v v i2 port 4, 5 (n-ch open drain) C0.3 to + 14 v output voltage v o C0.3 to v dd + 0.3 v high-level output current i oh per pin C10 ma total of all pins C30 ma low-level output current i ol per pin 30 ma total of all pins 220 ma operating ambient t a C40 to + 85 ?c temperature storage temperature t stg C65 to + 150 ?c caution if the absolute maximum rating of even one of the parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. be sure that these values are never exceeded when using the product. capacitance (t a = 25?c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out pins other than tested pins: 0 v 15 pf i/o capacitance c io 15 pf m pd75p0016 33 data sheet u10328ej3v1ds00 main system clock oscillation circuit characteristics (t a = C 40 to +85?c) resonator recommended parameter conditions min. typ. max. unit constants ceramic oscillation frequency v dd = 2.2 to 5.5 v 1.0 6.0 note 2 mhz resonator (f x ) note 1 oscillation after v dd has 4 ms stabilization time note 3 reached min. value of oscillation voltage range crystal oscillation frequency v dd = 2.2 to 5.5 v 1.0 6.0 note 2 mhz resonator (f x ) note 1 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 3 v dd = 2.2 to 5.5 v 30 ms external x1 input frequency v dd = 1.8 to 5.5 v 1.0 6.0 note 4 mhz clock (f x ) note 1 x1 input high-, v dd = 1.8 to 5.5 v 83.3 500 ns low-level widths (t xh , t xl ) notes 1. the oscillation frequency and x1 input frequency shown above indicate characteristics of the oscillation circuit only. for the instruction execution time, refer to ac characteristics. 2. if the oscillation frequency is 4.7 mhz < f x 6.0 mhz at 2.2 v v dd < 2.7 v of the supply voltage, please do not set processor clock control register (pcc) = 0011. if pcc = 0011, one machine cycle is less than 0.85 m s, falling short of the rated value of 0.85 m s. 3. the oscillation stablilization time is the time required for oscillation to be stabilized after v dd has been applied or stop mode has been released. 4. if the x1 input frequency is 4.19 mhz < f x 6.0 mhz at 1.8 v v dd < 2.7 v of the supply voltage, please do not set pcc = 0011. if pcc = 0011, one machine cycle time is less than 0.95 m s, falling short of the rated value of 0.95 m s. caution when using the main system clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance: keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. always keep the ground point of the capacitor of the oscillation circuit at the same potential as v dd . do not ground to a power supply pattern through which a high current flows. do not extract signals from the oscillation circuit. x1 x2 c1 c2 x1 x2 c1 c2 x1 x2 m pd75p0016 34 data sheet u10328ej3v1ds00 xt1 xt2 subsystem clock oscillation circuit characteristics (t a = C40 to +85?c) resonator recommended parameter conditions min. typ. max. unit constants crystal oscillation frequency v dd = 2.2 to 5.5 v 32 32.768 35 khz resonator (f xt ) note 1 oscillation v dd = 4.5 to 5.5 v 1.0 2 s stabilization time note 2 v dd = 2.2 to 5.5 v 10 s external xt1 input frequency v dd = 1.8 to 5.5 v 32 100 khz clock (f xt ) note 1 xt1 input high-, v dd = 1.8 to 5.5 v 5 15 m s low-level widths (t xth , t xtl ) notes 1. the oscillation frequency shown above indicate characteristics of the oscillation circuit only. for the instruction execution time, refer to ac characteristics. 2. the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied. caution when using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance: keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. always keep the ground point of the capacitor of the oscillation circuit at the same potential as v dd . do not ground to a power supply pattern through which a high current flows. do not extract signals from the oscillation circuit. the subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillation circuit. therefore, exercise utmost care in wiring the subsystem clock oscillation circuit. recommended oscillation circuit constant main system clock: ceramic resonator (t a = C40 to +85?c) oscillation circuit oscillation voltage manufacturer part number frequency constant (pf) range (v dd ) remark (mhz) c1 c2 min. (v) max. (v) tdk corp. ccr4.0mc32 4.0 10 10 2.3 5.5 caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. for this, it is necessary to directly contact the manufacturer of the resonator being used. xt1 xt2 c3 c4 r m pd75p0016 35 data sheet u10328ej3v1ds00 dc characteristics (t a = C40 to + 85?c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit low-level i ol per pin 15 ma output current total of all pins 150 ma high-level input v ih1 ports 2, 3, 8 2.7 v dd 5.5 v 0.7 v dd v dd v voltage 2.2 v dd 2.7 v 0.9 v dd v dd v v ih2 ports 0, 1, 6, 7, reset 2.7 v dd 5.5 v 0.8 v dd v dd v 2.2 v dd 2.7 v 0.9 v dd v dd v v ih3 ports 4, 5 (n-ch open drain) 2.7 v dd 5.5 v 0.7 v dd 13 v 2.2 v dd 2.7 v 0.9 v dd 13 v v ih4 x1, xt1 v dd C0.1 v dd v low-level input v il1 ports 2-5, 8 2.7 v dd 5.5 v 0 0.3 v dd v voltage 2.2 v dd 2.7 v 0 0.1 v dd v v il2 ports 0, 1, 6, 7, reset 2.7 v dd 5.5 v 0 0.2 v dd v 2.2 v dd 2.7 v 0 0.1 v dd v v il3 x1, xt1 0 0.1 v high-level output v oh sck, so, ports 2, 3, 6-8 v dd C0.5 v voltage i oh = C1.0 ma low-level output v ol1 sck, so, i ol = 15 ma, v dd = 4.5 to 5.5 v 0.2 2.0 v voltage ports 2-8 i ol = 1.6 ma 0.4 v v ol2 sb0, sb1 n-ch open drain 0.2 v dd v pull-up resistor 3 1 k w high-level input i lih1 v in = v dd pins other than x1 and xt1 3 m a leakage current i lih2 x1, xt1 20 m a i lih3 v in = 13 v ports 4, 5 (n-ch open drain) 20 m a low-level input i lil1 v in = 0 v pins other than ports 4, 5, x1 and xt1 C3 m a leakage current i lil2 x1, xt1 C20 m a i lil3 ports 4, 5 (n-ch open drain) when C3 m a input instruction is not executed ports 4, 5 (n-ch C30 m a open drain) when input v dd = 5.0 v C10 C27 m a instruction is v dd = 3.0 v C3 C8 m a executed high-level output i loh1 v out = v dd sck, so/sb0, sb1, ports 2, 3, 6-8 3 m a leakage current i loh2 v out = 13 v ports 4, 5 (n-ch open drain) 20 m a low-level output i lol v out = 0 v C3 m a leakage current internal pull-up r l v in = 0 v ports 0-3, 6-8 (except p00 pin) 50 100 200 k w resistor m pd75p0016 36 data sheet u10328ej3v1ds00 dc characteristics (t a = C40 to + 85?c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 v dd = 5.0 v 10 % note 3 3.7 11.0 ma v dd = 3.0 v 10 % note 4 0.73 2.2 ma i dd2 v dd = 5.0 v 10 % 0.92 2.6 ma v dd = 3.0 v 10 % 0.3 0.9 ma i dd1 v dd = 5.0 v 10 % note 3 2.7 8.0 ma v dd = 3.0 v 10 % note 4 0.57 1.7 ma i dd2 v dd = 5.0 v 10 % 0.9 2.5 ma v dd = 3.0 v 10 % 0.28 0.8 ma i dd3 v dd = 3.0 v 10 % 42 126 m a v dd = 2.5 v 10 % 23 69 m a v dd = 3.0 v, t a = 25 ?c 42 84 m a v dd = 3.0 v 10 % 39 117 m a v dd = 3.0 v, t a = 25 ?c 39 78 m a i dd4 v dd = 3.0 v 10 % 8.5 25 m a v dd = 2.5 v 10 % 5.0 15 m a v dd = 3.0 v, t a = 25 ?c 8.5 17 m a v dd = 3.0 v 10 % 3.5 12 m a v dd = 3.0 v, t a = 25 ?c 3.5 7 m a i dd5 v dd = 5.0 v 10 % 0.05 10 m a v dd = 3.0 v 10 % 0.02 5 m a t a = 25 ?c 0.02 3 m a notes 1. the current flowing through the internal pull-up resistor is not included. 2. including the case when the subsystem clock oscillates. 3. when the device operates in high-speed mode with the processor clock control register (pcc) set to 0011. 4. when the device operates in low-speed mode with pcc set to 0000. 5. when the device operates on the subsystem clock, with the system clock control register (scc) set to 1001 and oscillation of the main system clock stopped. 6. when the suboscillation circuit control register (sos) is set to 0000. 7. when sos is set to 0010. 8. when sos is set to 00 1, and the suboscillation circuit feedback resistor is not used ( : dont care). 6.0 mhz note 2 crystal oscillation c1 = c2 = 22 pf 4.19 mhz note 2 crystal oscillation c1 = c2 = 22 pf low current consumption mode note 7 low current dissipation mode note 7 xt1 = 0v note 8 stop mode 32.768 khz note 5 crystal oscillation halt mode halt mode halt mode low- voltage mode note 6 low- voltage mode note 6 m pd75p0016 37 data sheet u10328ej3v1ds00 ac characteristics (t a = C40 to + 85?c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit cpu clock cycle t cy v dd = 2.7 to 5.5 v 0.67 64 m s time note 1 0.85 64 m s (minimum instruction v dd = 2.7 to 5.5 v 0.67 64 m s execution time = 1 v dd = 1.8 to 5.5 v 0.95 64 m s machine cycle) operates with subsystem clock 114 122 125 m s ti0 input frequency f ti v dd = 2.7 to 5.5 v 0 1.0 mhz 0 275 khz ti0 high-, low-level t tih , t til v dd = 2.7 to 5.5 v 0.48 m s widths 1.8 m s interrupt input high-, t inth , int0 im02 = 0 note 2 m s low-level widths t intl im02 = 1 10 m s int1, 2, 4 10 m s kr0-kr7 10 m s reset low-level width t rsl 10 m s notes 1. the cycle time of the cpu clock ( f ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (scc), and processor clock control register (pcc). the figure on the right shows the supply voltage v dd vs. cycle time t cy characteristics when the device operates with the main system clock. 2. 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). with external clock with ceramic oscillator or crystal resonator operates with main system clock 0.5 0 supply voltage v dd [v] cycle time t cy ( s) 12 3456 1 2 3 4 5 6 60 64 (with main system clock) t cy vs v dd m 0.95 0.85 0.67 1.8 2.2 2.7 5.5 operation guaranteed range remark shaded area indicates operation when external clock is used. m pd75p0016 38 data sheet u10328ej3v1ds00 serial transfer operation 2-wire and 3-wire serial i/o modes (sck internal clock output): (t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-, low-level widths t kl1 ,v dd = 2.7 to 5.5 v t kcy1 /2C50 ns t kh1 t kcy1 /2C150 ns si note 1 setup time t sik1 v dd = 2.7 to 5.5 v 150 ns (vs. sck - ) 500 ns si note 1 hold time t ksi1 v dd = 2.7 to 5.5 v 400 ns (vs. sck - ) 600 ns sck ? so note 1 output t kso1 r l = 1 k w note 2 v dd = 2.7 to 5.5 v 0 250 ns delay time c l = 100 pf 0 1000 ns notes 1. read as sb0 or sb1 when using the 2-wire serial i/o mode. 2. r l and c l respectively indicate the load resistance and load capacitance of the so output line. 2-wire and 3-wire serial i/o modes (sck external clock input): (t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-, low-level widths t kl2 ,v dd = 2.7 to 5.5 v 400 ns t kh2 1600 ns si note 1 setup time t sik2 v dd = 2.7 to 5.5 v 100 ns (vs. sck - ) 150 ns si note 1 hold time t ksi2 v dd = 2.7 to 5.5 v 400 ns (vs. sck - ) 600 ns sck ? so note 1 output t kso2 r l = 1 k w note 2 v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf 0 1000 ns notes 1. read as sb0 or sb1 when using the 2-wire serial i/o mode. 2. r l and c l respectively indicate the load resistance and load capacitance of the so output line. m pd75p0016 39 data sheet u10328ej3v1ds00 sbi mode (sck internal clock output (master)): (t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy3 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-, low-level widths t kl3 v dd = 2.7 to 5.5 v t kcy3 /2C50 ns t kh3 t kcy3 /2C150 ns sb0, 1 setup time t sik3 v dd = 2.7 to 5.5 v 150 ns (vs. sck - ) 500 ns sb0, 1 hold time (vs. sck - )t ksi3 t kcy3 /2 ns sck ? sb0, 1 output t kso3 r l = 1 k w note v dd = 2.7 to 5.5 v 0 250 ns delay time c l = 100 pf 0 1000 ns sck - ? sb0, 1 t ksb t kcy3 ns sb0, 1 ? sck t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns note r l and c l respectively indicate the load resistance and load capacitance of the sb0 and 1 output lines. sbi mode (sck external clock input (slave)): (t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy4 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-, low-level widths t kl4 v dd = 2.7 to 5.5 v 400 ns t kh4 1600 ns sb0, 1 setup time t sik4 v dd = 2.7 to 5.5 v 100 ns (vs. sck - ) 150 ns sb0, 1 hold time (vs. sck - )t ksi4 t kcy4 /2 ns sck ? sb0, 1 output t kso4 r l = 1 k w note v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf 0 1000 ns sck - ? sb0, 1 t ksb t kcy4 ns sb0, 1 ? sck t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns note r l and c l respectively indicate the load resistance and load capacitance of the sb0 and 1 output lines. m pd75p0016 40 data sheet u10328ej3v1ds00 v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.) ac timing test points (except x1 and xt1 inputs) clock timing ti0 timing 1/f ti t til t tih ti0 1/f x t xl t xh v dd C 0.1 v 0.1 v x1 input 1/f xt t xtl t xth v dd C 0.1 v 0.1 v xt1 input m pd75p0016 41 data sheet u10328ej3v1ds00 serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode sck sb0, 1 t kcy1, 2 t kl1, 2 t kh1, 2 t kso1, 2 t sik1, 2 t ksi1, 2 t kcy1, 2 sck output data so input data si t sik1, 2 t kso1, 2 t kl1, 2 t kh1, 2 t ksi1, 2 m pd75p0016 42 data sheet u10328ej3v1ds00 serial transfer timing bus release signal transfer command signal transfer interrupt input timing reset input timing sck sb0, 1 t kcy3, 4 t sik3, 4 t kso3, 4 t ksi3, 4 t sbk t sbh t sbl t ksb t kh3, 4 t kl3, 4 sck sb0, 1 t kcy3, 4 t sik3, 4 t kso3, 4 t kl3, 4 t kh3, 4 t ksi3, 4 t sbk t ksb int0, 1, 2, 4 kr0-7 t intl t inth reset t rsl m pd75p0016 43 data sheet u10328ej3v1ds00 stop mode data retention mode internal reset operation operation mode stop instruction execution halt mode v dd reset t wait t srel stop mode data retention mode operation mode halt mode t srel t wait stop instruction execution v dd standby release signal (interrupt request) data retention characteristics of data memory in stop mode and at low supply voltage (t a = C40 to +85?c) parameter symbol conditions min. typ. max. unit release signal setup time t srel 0 m s oscillation stabilization t wait released by reset 2 15 /f x ms wait time note 1 released by interrupt request note 2 ms notes 1. the oscillation stabilization wait time is the time during which the cpu stops operating to prevent unstable operation when oscillation is started. 2. set by the basic interval timer mode register (btm). (refer to the table below.) btm3 btm2 btm1 btm0 wait time f x = 4.19 mhz f x = 6.0 mhz C0002 20 /f x (approx. 250 ms) 2 20 /f x (approx. 175 ms) C0112 17 /f x (approx. 31.3 ms) 2 17 /f x (approx. 21.8 ms) C1012 15 /f x (approx. 7.81 ms) 2 15 /f x (approx. 5.46 ms) C1112 13 /f x (approx. 1.95 ms) 2 13 /f x (approx. 1.37 ms) data retention timing (when stop mode released by reset) data retention timing (standby release signal: when stop mode released by interrupt signal) m pd75p0016 44 data sheet u10328ej3v1ds00 dc programming characteristics (t a = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0v) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 other than x1, x2 pins 0.7 v dd v dd v v ih2 x1, x2 v dd C 0.5 v dd v input voltage, low v il1 other than x1, x2 pins 0 0.3 v dd v v il2 x1, x2 0 0.4 v input leakage current i li v in = v il or v ih 10 m a output voltage, high v oh i oh = C 1 ma v dd C 1.0 v output voltage, low v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 30 ma v pp supply current i pp md0 = v il , md1 = v ih 30 ma cautions 1. keep v pp to within +13.5 v, including overshoot. 2. apply v dd before v pp and turn it off after v pp . ac programming characteristics (t a = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol note 1 conditions min. typ. max. unit address setup time note 2 t as t as 2 m s (vs. md0 ) md1 setup time (vs. md0 )t m1s t oes 2 m s data setup time (vs. md0 )t ds t ds 2 m s address hold time note 2 t ah t ah 2 m s (vs. md0 - ) data hold time (vs. md0 - )t dh t dh 2 m s md0 - ? data output float t df t df 0 130 ns delay time v pp setup time (vs. md3 - )t vps t vps 2 m s v dd setup time (vs. md3 - )t vds t vcs 2 m s initial program pulse width t pw t pw 0.95 1.0 1.05 ms additional program pulse width t opw t opw 0.95 21.0 ms md0 setup time (vs. md1 - )t m0s t ces 2 m s md0 ? data output delay time t dv t dv md0 = md1 = v il 1 m s md1 hold time (vs. md0 - )t m1h t oeh t m1h + t m1r 3 50 m s2 m s md1 recovery time (vs. md0 ) t m1r t or 2 m s program counter reset time t pcr 10 m s x1 input high-, low-level width t xh , t xl 0.125 m s x1 input frequency f x 4.19 mhz initial mode set time t 1 2 m s md3 setup time (vs. md1 - )t m3s 2 m s md3 hold time (vs. md1 )t m3h 2 m s md3 setup time (vs. md0 )t m3sr when program memory is read 2 m s address note 2 ? data output t dad t acc when program memory is read 2 m s delay time address note 2 ? data output t had t oh when program memory is read 0 130 ns hold time md3 hold time (vs. md0 - )t m3hr when program memory is read 2 m s md3 ? data output float t dfr when program memory is read 2 m s delay time notes 1. symbol of corresponding m pd27c256a 2. the internal address signal is incremented by one at the rising edge of the fourth x1 input and is not connected to a pin. m pd75p0016 45 data sheet u10328ej3v1ds00 v pp v dd v dd +1 v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 v dd v pp data output t vps t vds t xh t xl t dad t had t dv t dfr t m3hr t i t pcr t m3sr data output v pp v dd v dd +1 v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 v pp v dd data input t vps t vds t xh t xl t i t ds t dh t pw t dv t df t m1r t m0s t ds t dh t opw t ah t as t m1s t m1h t pcr t m3s t m3h data input data input data output program memory write timing program memory read timing m pd75p0016 46 data sheet u10328ej3v1ds00 10. characteristics curves (reference value) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 01234 suppl y volta g e v dd ( v ) i dd vs v dd (main system clock : 6.0 mhz crystal resonator) supply current i dd (ma) 5678 pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 main system clock halt mode +32-khz oscillation subsystem clock operation mode (sos.1 = 0) subsystem clock halt mode (sos.1 = 0) and main system clock stop mode +32-khz oscillation (sos.1 = 0) subsystem clock halt mode (sos.1 = 1) and main system clock stop mode +32-khz oscillation (sos.1 = 1) x1 crystal resonator 6.0 mhz crystal resonator 32.768 khz x2 xt1 330 k w 22 pf 22 pf 22 pf 22 pf xt2 (t a = 25?c) m pd75p0016 47 data sheet u10328ej3v1ds00 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 x1 x2 xt1 330 k w 22 pf 22 pf 22 pf 22 pf xt2 supply voltage v dd (v) i dd vs v dd (main system clock : 4.19 mhz crystal resonator) supply current i dd (ma) main system clock halt mode +32-khz oscillation subsystem clock operation mode (sos.1 = 0) subsystem clock halt mode (sos.1 = 0) and main system clock stop mode +32-khz oscillation (sos.1 = 0) subsystem clock halt mode (sos.1 = 1) and main system clock stop mode +32-khz oscillation (sos.1 = 1) crystal resonator 4.19 mhz crystal resonator 32.768 khz (t a = 25?) m pd75p0016 48 data sheet u10328ej3v1ds00 11. package drawings 42pin plastic shrink dip (600 mil) item millimeters inches a b c f g h i j k 39.13 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. 0.17 15.24 (t.p.) 5.08 max. n 0.9 min. r 1.541 max. 0.070 max. 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.600 (t.p.) 0.007 0.070 (t.p.) p42c-70-600a-1 a c d g notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. d 0.50?.10 0.020 m 0.25 0.010 +0.10 ?.05 0~15 0~15 +0.004 ?.003 +0.004 ?.005 m k n l 13.2 0.520 2) item "k" to center of leads when formed parallel. 42 1 22 21 l m r b f h j i m pd75p0016 49 data sheet u10328ej3v1ds00 44 pin plastic qfp ( 10) s44gb-80-3bs item millimeters inches n p q 0.125?.075 0.10 2.7 0.004 0.106 0.005?.003 note each lead centerline is located within 0.16 mm (0.007 inch) of its true position (t.p.) at maximum material condition. j i h n a 13.2?.2 0.520 +0.008 ?.009 b 10.0?.2 0.394 +0.008 ?.009 c 10.0?.2 0.394 +0.008 ?.009 d 13.2?.2 0.520 +0.008 ?.009 f g h 1.0 0.37 1.0 0.039 0.039 0.015 +0.003 ?.004 i j k 0.8 (t.p.) 1.6?.2 0.16 0.007 0.031 (t.p.) 0.063?.008 l 0.8?.2 0.031 +0.009 ?.008 m 0.17 0.007 +0.002 ?.003 s 3.0 max. 0.119 max. r3 3 +7 ? +0.08 ?.07 +0.06 ?.05 +7 ? detail of lead end q f g k m l r m 33 34 22 44 1 12 11 23 s p cd a b m pd75p0016 50 data sheet u10328ej3v1ds00 12. recommended soldering conditions solder the m pd75p0016 under the following recommended conditions. for the details on the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for the soldering methods and conditions other than those recommended, consult nec. table 12-1. soldering conditions of surface mount type m pd75p0016gb-3bs-mtx: 44-pin plastic qfp (10 10 mm, 0.8-mm pitch) symbol of soldering method soldering conditions recommended condition infrared reflow package peak temperature: 235?c, time: 30 seconds max. (210?c min.), ir35-00-3 number of times: 3 max. vps package peak temperature: 215?c, time: 40 seconds max. (200?c min.), vp15-00-3 number of times: 3 max. wave soldering soldering bath temperature: 260?c max., time: 10 seconds max., ws60-00-1 number of times: 1 preheating temperature: 120?c max. (package surface temperature) partial heating pin temperature: 300?c max., time: 3 seconds max. (per side of device) C caution do not use two or more soldering methods in combination (except the partial heating method). table 12-2. soldering conditions of insertion type m pd75p0016cu: 42-pin plastic shrink dip (600 mil, 1.778-mm pitch) soldering method soldering conditions wave soldering (pin only) soldering bath temperature: 260?c max., time: 10 seconds max. partial heating pin temperature: 300?c max., time: 3 seconds max. (per pin) caution apply wave soldering to the pins only. be careful not to allow solder jet to come into direct contact with the body of the chip. m pd75p0016 51 data sheet u10328ej3v1ds00 appendix a. function list of m pd75008, 750008, 75p0016 (1/2) item m pd75008 m pd750008 m pd75p0016 program memory mask rom mask rom one-time prom 0000h - 1f7fh 0000h - 1fffh 0000h - 3fffh (8064 8 bits) (8192 8 bits) (16384 8 bits) data memory 000h - 1ffh (512 4 bits) cpu 75x standard cpu 75xl cpu general register 4 bits 8 or 8 bits 4 (4 bits 8 or 8 bits 4) 4 banks instruction when main system ? 0.95, 1.91, 15.3 m s ? 0.95, 1.91, 3.81, 15.3 m s (at 4.19 mhz operation) execution clock is selected (at 4.19 mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (at 6.0 mhz operation) time when subsystem 122 m s (at 32.768 khz operation) clock is selected stack sbs register none yes sbs.3 = 1: mk i mode selected sbs.3 = 0: mk ii mode selected stack area 000h - 0ffh n00h - nffh (n = 0, 1) stack operation of 2-byte stack in mk i mode: 2-byte stack subroutine call in mk ii mode: 3-byte stack instruction instructions bra !addr1 unusable in mk i mode: unusable calla !addr1 in mk ii mode: usable movt xa, @bcde usable movt xa, @bcxa br bcde br bcxa call !addr 3 machine cycles mk i mode: 3 machine cycles mk ii mode: 4 machine cycles callf !faddr 2 machine cycles mk i mode: 2 machine cycles mk ii mode: 3 machine cycles timer 3 channels 4 channels ? basic interval timer: ? basic interval timer/watchdog timer: 1 channel 1 channel ? 8-bit timer/event counter: 1 channel ? 8-bit timer/event counter: ? 8-bit timer counter: 1 channel 1 channel ? watch timer: 1 channel ? watch timer: 1 channel clock output (pcl) ? f , 524, 262, 65.5 khz ? f , 524, 262, 65.5 khz (main system clock: (main system clock: at 4.19 mhz operation) at 4.19 mhz operation) ? f , 750, 375, 93.8 khz (main system clock: at 6.0 mhz operation) buz output (buz) ? 2 khz ? 2, 4, 32 khz (main system clock: at 4.19 mhz operation) ? 2.93, 5.86, 46.9 khz (main system clock: at 6.0 mhz operation) m pd75p0016 52 data sheet u10328ej3v1ds00 (2/2) item m pd75008 m pd750008 m pd75p0016 serial interface compatible with 3 kinds of mode ? 3-wire serial i/o mode ... msb/lsb-first can be switched ? 2-wire serial i/o mode ? sbi mode sos register feedback resistor on-chip feedback resistor on chip cut flag (sos.0) specifiable by mask option sub oscillator current none on chip cut flag (sos.1) register bank selection register none yes (rbs) standby release by int0 not possible possible vectored interrupt external: 3 internal: 3 external: 3 internal: 4 processor clock control register pcc = 0, 2, 3 can be used pcc = 0 to 3 can be used (pcc) supply voltage v dd = 2.7 to 6.0 v v dd = 2.2 to 5.5 v operating ambient temperature t a = C40 to +85?c package ? 42-pin plastic shrink dip (600 mil, 1.778-mm pitch) ? 44-pin plastic qfp (10 10 mm, 0.8-mm pitch) m pd75p0016 53 data sheet u10328ej3v1ds00 appendix b. development tools the following development tools are provided for system development using the m pd75p0016. the 75xl series uses a common relocatable assembler, in combination with a device file matching each machine. ra75x relocatable assembler host machine part number os supply medium (product name) pc-9800 series ms-dos tm 3.5" 2hd m s5a13ra75x ver.3.30 to ver.6.2 note ibm pc/at tm refer to os for 3.5" 2hc m s7b13ra75x or compatible ibm pcs device file host machine part number os supply medium (product name) pc-9800 series ms-dos 3.5" 2hd m s5a13df750008 ver.3.30 to ver.6.2 note ibm pc/at refer to os for 3.5" 2hc m s7b13df750008 or compatible ibm pcs note ver. 5.00 and the upper versions of ver. 5.00 are provided with a task swap function, but it does not work with this software. remark the operation of the assembler and device file is guaranteed only on the above host machines and oss. m pd75p0016 54 data sheet u10328ej3v1ds00 prom write tools hardware pg-1500 a stand-alone system can be configured of a single-chip microcomputer with on-chip prom when connected to an auxiliary board (companion product) and a programmer adapter (separately sold). alternatively, a prom programmer can be operated on a host machine for programming. in addition, typical proms in capacities ranging from 256 k to 4 m bits can be programmed. pa-75p008cu this is a prom programmer adapter for the m pd75p0016cu/gb. it can be used when connected to a pg-1500. pa-75p0016gb this is a prom programmer adapter for the m pd75p0016gb-3bs-mtx. it can be used when connected to a pg-1500. software pg-1500 controller establishes serial and parallel connections between the pg-1500 and a host machine for host- machine control of the pg-1500. host machine part number os supply medium (product name) pc-9800 series ms-dos 3.5" 2hd m s5a13pg1500 ver.3.30 to ver.6.2 note ibm pc/at refer to os for 3.5" 2hd m s7b13pg1500 or compatible ibm pcs note ver. 5.00 and the upper versions of ver. 5.00 are provided with a task swapping function, but it does not work with this software. remark operation of the pg-1500 controller is guaranteed only on the above host machine and oss. m pd75p0016 55 data sheet u10328ej3v1ds00 debugging tools in-circuit emulators (ie-75000-r and ie-75001-r) are provided as program debugging tools for the m pd75p0016. various system configurations using these in-circuit emulators are listed below. hardware ie-75000-r note 1 the ie-75000-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75x or 75xl series products. for development of the m pd750008 subseries, the ie-75000-r is used with a separately sold emulation board ie- 75300-r-em and emulation probe ep-75008cu-r or ep-75008gb-r. these products can be applied for highly efficient debugging when connected to a host machine and prom programmer. the ie-75000-r can include a connected emulation board (ie-75000-r-em). ie-75001-r the ie-75001-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75x or 75xl series products. the ie-75001-r is used with a separately sold emulation board (ie-75300-r-em) and emulation probe ep- 75008cu-r or ep-75008gb-r. these products can be applied for highly efficient debugging when connected to a host machine and prom programmer. ie-75300-r-em this is an emulation board for evaluating application systems that use the m pd750008 subseries. it is used in combination with the ie-75000-r or ie-75001-r in-circuit emulator. ep-75008cu-r this is an emulation probe for the m pd75p0016cu. when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. ep-75008gb-r this is an emulation probe for the m pd75p0016gb. ev-9200g-44 when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. it includes a 44-pin conversion socket (ev-9200g-44) to facilitate connections with various target systems. software ie control program this program can control the ie-75000-r or ie-75001-r on a host machine when connected to the ie-75000-r or ie-75001-r via an rs-232-c or centronics i/f. host machine part number os supply medium (product name) pc-9800 series ms-dos 3.5" 2hd m s5a13ie75x ver.3.30 to ver.6.2 note 2 ibm pc/at refer to os for 3.5" 2hc m s7b13ie75x or compatible ibm pcs notes 1. this is a service part provided for maintenance purpose only. 2. ver. 5.00 and the upper versions of ver. 5.00 are provided with a task swapping function, but it does not work with this software. remarks 1. operation of the ie control program is guaranteed only on the above host machine and oss. 2. the m pd75000 subseries consists of the m pd750004, 750006, 750008 and 75p00016. m pd75p0016 56 data sheet u10328ej3v1ds00 os for ibm pcs the following operating systems for the ibm pc are supported. os version pc dos tm ver.3.1 to ver.6.3 j6.1/v note to j6.3/v note ms-dos ver.5.0 to ver.6.22 5.0/v note to j6.2/v note ibm dos tm j5.02/v note note supports english version only. caution ver 5.0 and above include a task swapping function, but this software is not able to use that function. m pd75p0016 57 data sheet u10328ej3v1ds00 appendix c. related documents some of the following related documents are preliminary. this document, however, is not indicated as preliminary. device related documents document name document no. japanese english m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) u10738j u10738e data sheet m pd75p0016 data sheet u10328j this document m pd750008 users manual u10740j u10740e m pd750008, 750108 instruction list u11456j C 75xl series selection guide u10453j u10453e development tool related documents document name document no. japanese english ie-75000 r/ie-75001-r users manual eeu-846 eeu-1416 ie-75300-r-em users manual u11354j u11354e ep-750008cu-r users manual eeu-699 eeu-1317 ep-750008gb-r users manual eeu-698 eeu-1305 pg-1500 users manual u11940j u11940e ra75x assembler package operation u12622j u12622e users manual language u12385j u12385e pg-1500 controller users manual pc-9800 series eeu-704 eeu-1291 (ms-dos) base ibm pc series eeu-5008 u10540e (pc dos) base other documents document name document no. japanese english semiconductor selection guide products & package (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices electrostatic c11892j c11892e discharge (esd) guide for products related to microcomputer : other companies c11416j C caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents. hardware software m pd75p0016 58 data sheet u10328ej3v1ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools includ- ing work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immedi- ately after power-on for devices having reset function. m pd75p0016 59 data sheet u10328ej3v1ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7 m pd75p0016 qtop is a trademark of nec corporation. ms-dos is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of august, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). |
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